The present invention relates to a semiconductor memory device, and more particularly to an electrostatic discharge protection circuit of a semiconductor memory device that protects the gate oxide of internal circuit elements against static electricity.
With the growing popularity of high integration in semiconductor technologies, the size of memory chips is decreasing, and electrostatic discharge (ESD) protection circuits, used to protect the internal circuit of the memory chip against static electricity, are becoming more complicated.
Moreover, in order to improve the operation of the memory chip, the gate oxide of internal circuit elements included in a semiconductor memory device is becoming thinner, which leads to a reduction in the breakdown voltage of the gate oxide of internal circuit elements.
Disadvantageously, for protection of the thin gate oxide, a protection circuit must be designed such that the driving voltage of the ESD protection element is smaller than the breakdown voltage of the gate oxide.
Referring to FIG. 1, the conventional semiconductor memory device is constructed such that a power clamp element GGN1 and a decoupling capacitor C1 are connected in parallel between a power pad 10 and a ground pad 20 while a power clamp element GGN2 is connected between the ground pads 20 and 30 in order to achieve ESD protection. The ground pads 20 and 30 are respectively supplied with different ground voltages.
Among semiconductor memory devices having the above described structure, an ESD protection circuit 50 is included in a fast and highly integrated semiconductor memory device employing a thin gate oxide. However, when ESD is generated, the ESD protection circuit 50 may cause erroneous operations due to a low electrostatic voltage. This is because the voltage held between the power pad 10 and the ground pad 30 increases by as much as the breakdown voltage of the gate oxide of elements in an internal circuit 40 using a power voltage VDD.
For example, referring to FIG. 2, the driving voltage Vt1 of the ESD protection circuit 50 is measured to be about 7.2V in a condition that a characteristic of the ESD protection circuit 50 shown in FIG. 1 is measured by using transmission line pulse (TLP) equipment, which shows a snapback current-voltage characteristic curve.
In this state, when the characteristics of voltage and current between the power pad 10 and the ground pad 30 are measured with the TLP equipment during an ESD test, as shown by the solid line in FIG. 3, the voltage V1 held between the power pad 10 and the ground pad 30 is measured to be about 10V. In addition, as shown by the dotted line in FIG. 3, a leakage current I1 is produced between the power pad 10 and the ground pad 30 when the voltage V1 is about 8.5V.
In this case, if the leakage current I1 is produced between the power pad 10 and the ground pad 30 when the voltage V1 held between the power pad 10 and the ground pad 30 is about 8.5V during the ESD test, the gate oxide of the elements in the internal circuit 40 is broken down.
As shown in FIG. 4, such a result can be understood by the fact that the breakdown voltage TLP-BVOX of the gate oxide of the elements in the internal circuit 40 having a gate oxide width GOP of 35 Å is measured to be about 8V when the breakdown voltage TLP-BVOX of the gate oxide of the elements in the internal circuit 40 is measured by using the TLP equipment.
In the conventional semiconductor memory device, the driving voltage of the ESD protection circuit 50 rises when ESD is generated. The driving voltage is increased due to the power line resistor R1 connected between the heterogeneous ground pads 20 and 30 and the capacitor C1 connected between the power pad 10 and the ground pad 20.
Referring to Table 1 below, if the resistance of the power line resistor R1 is 0.5Ω and the capacitance of the capacitor C1 is 1 nF, the driving voltage Vt1 of the ESD protection circuit 50 is maintained at about 7.6V regardless of the generation of ESD.
TABLE 1R1 = 0.5 ΩR1 = 3.0 ΩC1 = 1 nFC1 = 10 nFC1 = 30 nFC1 = 1 nFC1 = 10 nFC1 = 30 nFVt1 7.6 V 7.8 V 8.0 V 8.1 V 9.3 V10.6 VIt10.19 A0.62 A1.06 A0.19 A0.62 A1.06 A
Here, It1 denotes the current flowing between the power pad 10 and the ground pad 30.
On the other hand, if the resistance of the power line resistor R1 is 3.0Ω and the capacitance of the capacitor C1 is 30 nF, the driving voltage Vt1 of the ESD protection circuit 50 rises to about 10.6V.
The power line resistor R1 and the capacitor C1 may result in ESD generation. If this is the case, the driving voltage Vt1 of the ESD protection circuit 50 may be higher than the voltage of the gate oxide of the elements in the internal circuit 40. The thin gate oxide of the elements in the internal circuit 40 may therefore break down due to ESD.